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lipingx's avatar
lipingx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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EP4CE15U14A7N DDR2 interface

Use bank 2, 3, 4 for ddr2: micron MT47H128M16RT-25E:C TR question: 1) only 1 DQS pin marked in pin list, how to handle LDQS and UDOS? 2) The DDR2 DQS pin is differential, but FPGA is single end, h...
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  • FvM's avatar
    FvM
    2 years ago

    Hi,

    just read the device manual and pin list thoroughly.

    Post #1 is quoting the DQS for x16/x18 column, however as clearly written in the device manual and stated in post #2, DDR2 RAM has to use x8/x9 DQS configuration. There are more DQS pins available for x8/x9, e.g. M7 and T7 in bottom banks B3/B4.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


For your information, Cyclone IV devices do not support differential strobe pins.

This feature is optional in DDR2 SDRAM device.


Please my answer to your question in point below:


1) only 1 DQS pin marked in pin list, how to handle LDQS and UDOS?

  • DDR2 SDRAM interfaces use x8 mode DQS group regardless of the interface width.
  • For wider interface, you can use multiple x8 DQ groups to achieve the desired width requirement.


2) The DDR2 DQS pin is differential, but FPGA is single end, how to handle?

  • The DDR2 SDRAM can support single-ended mode.
  • You may refer to memory datasheet in page 84 to disable the DQS# ball.


3) For DM pin, DM5B0 is for LDM or UDM?

  • LDM is DM for lower byte DQ [7:0] and UDM is DM for upper byte DQ[15:8]
  • Use multiple x8 DQ groups to achieve the desired width requirement.


Regards,

Adzim