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Honored Contributor
Honored ContributorEP3C LVDS : external PLL
Hello everyone, I have specific question on configuring CycloneIII LVDS with external PLL. I’ve searched thru the forum but did not find info relevant to my case I need to run two simil...
Altera_ForumHonored Contributor
Honored ContributorAlright, converting dialog to monologue - answering my own question :)
In order to share one PLL between two different TX LVDS blocks you need to apply the same approach as with sharing one PLL between Rx and Tx blocks - connect lvds_0_tx_inst.pll_areset and lvds_1_tx_inst.pll_areset ports to the same reset signal; connect lvds_0_tx_inst.tx_inclock and lvds_1_tx_inst.tx_inclock ports to the same clock source. In this case the fitter will merge two LVDS TX Plls into one pll, look for "Info: Successfully merged PLL <pll_0> and PLL <pll_1>" message in the processing log
