"end of initialization" reset

Excerpt from my post at http://www.alteraforum.com/forum/showthread.php?p=4560#post4560:

If you are using Quartus integrated synthesis, then in the Quartus handbook see Volume 1, Section III, Chapter 8. Read the "State Machine Processing" section and the following sections. The handbook tells you how you can optionally encode your states manually (there's also a VHDL template in the text editor for this).

For automatic one-hot encoding (and I'm guessing for other encodings that are not user-specified), this section of the handbook says, "Quartus II integrated synthesis encodes the initial state with all zeros for the state machine power-up because all device registers power up to a low value." I didn't know whether "the initial state" means the first state listed in the type definition or if synthesis determines it from a reset signal in the state machine to make the power-up reset state match the one controlled by the reset signal. I did an experiment and found that the state forced by an asynchronous reset signal (I didn't try a synchronous reset signal) is always the one that gets encoded with all state bits low when "State Machine Processing" is set to "Auto". The all-bits-low state isn't necessarily the first one listed in the type definition.

Check the Analysis & Synthesis report for the actual state encoding. It is shown in messages and in a table.