Embed sdc constraint in vhdl design file - help needed

--- Quote Start ---

Just had a thought, but in your code you tie the attribute to a port that would already exist. In the OPs code technically the entities havent been instantiated yet, so their names may not exist in the name table yet (or whatever altera does with them). Im not entirely sure this is the case, because SDC constraints arent usually applied until fitter or timing stages. But have you tried putting the constraints inside the entities rather than the architecture above?

--- Quote End ---

The attribute is tied to the Architecture, although tying it to the Entity is also an option.

The same technique is used in AHDL files where you can (could as .tdf have gone out of style) add Timing Analyser commands at the top of the file. They only get evaluated after Analysis & Synthesis.

E.g: the dcfifo

OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SYNCHRONIZER_IDENTIFICATION=OFF;SYNCHRONIZATION_REGISTER_CHAIN_LENGTH = 3;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=d103;suppress_da_rule_internal=R105;{-to rdemp_eq_comp_lsb_aeb} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rdemp_eq_comp_lsb_aeb} POWER_UP_LEVEL=HIGH;{-to rdemp_eq_comp_msb_aeb} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rdemp_eq_comp_msb_aeb} POWER_UP_LEVEL=HIGH;{-to rs_dgwp_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to wrfull_eq_comp_lsb_mux_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to wrfull_eq_comp_msb_mux_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to wrptr_g} suppress_da_rule_internal=S102;{-to wrptr_g} POWER_UP_LEVEL=LOW;{-to ws_dgrp_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;-name CUT ON -from rdptr_g -to ws_dgrp|dffpipe_re9:dffpipe17|dffe18a;-name SDC_STATEMENT ""set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_re9:dffpipe17|dffe18a* "";-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe_qe9:dffpipe14|dffe15a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_qe9:dffpipe14|dffe15a* """;

even has constraints for both TAn and TQ.

Also moving the multicycle_path exception into the (lower) entities is not possible as the exception targets both entities.