Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI am trying your idea but it is the first time I am unsing the tap signal interface and I am not succeeding. I read the literature on Altera but I still don't understand my mistakes. First, a word about my design. I added to the CIII_NiosII_Small design provided by Altera a BUTTON[3..0] signal as another entry. On the SignalTap II Embedded Logic Analyzer, I added the four signal (corresponding to each button), the clock and entered the hardware setup (USB).
Now I have errors from the Analyzer : ISED_PROGRAM_DEVICE CAUSE: You attempted to run the SignalTap II Logic Analyzer, but the current design does not match the design programmed in the device. ACTION: Program the device with the current design, and re-attempt to run the run the SignalTap II Logic Analyzer. And from Quartus : Error: Current license file does not support incremental compilation Can you help me ?