Dynamic Phase Shift PLL - Cyclon IV E

The dynamic phase shift capability isn't documented as clearly as it could be. I'm not sure how anyone has gotten it working by following the docs. I had to run the PHASESTEP, PHASEDONE, and SCANCLK signals out to a scope to see what was happening.

The timing diagram in the Cyclone IV device handbook (Oct 2012) looks like this:

http://www.ke5fx.com/doc.png

But what actually happens is that while PHASEDONE goes low on SCANCLK rising, it immediately goes high on the next falling edge:

http://www.ke5fx.com/TDS_phaseadj.png

As a result, you cannot build a state machine that watches for PHASEDONE falling ("Deassert PHASESTEP after PHASEDONE goes low") unless you drive it from the negative edge of SCANCLK. Synchronous logic on the positive edge of SCANCLK will never see PHASEDONE low unless it gets (temporarily) lucky with the timing. Or, it might be dependent on the relationship between the VCO and output clock in question, in which case it's a bug.

So if you're still struggling with this, try the other clock edge.