Dynamic Partial Reconfiguration & Direct Bitstream File Manipulation

Thank you Alex,

I will check Cyclone and Stratix for DPR.

and

Yes, I am reffering to the bitstream configuration file. In this case is the .sof file.

The reasons for that rely on a research area called Evolvable Hardware.

In a few words, we need to run the following loop:

1-.sof file generation;

2-download the bitstream file configuration to the development board;

3-circuit/system evalutation;

4-if termination condition reached go to step 1;

5-final circuit/system generated.

This loop needs to be executed in a "population" of circuit-candidates for each circuit, dozens of times, i.e., population# 1,# 2, ..., until final population.

In this scenario, the time spent is intractable if we need to synthesize, place and route and generate each .sof file (each circuit-candidate) for just one population.

Xilinx JBits, for example is a tool that allows direct bitstream manipulation, but there are some problems regarding opening documentation, other restriction problems regarding the type of FPGA device to be bitstream-file-edited, and the tool itself I suspect it is discontinued.

So, if I find an Altera or other vendor specific tool that allows me the processing of step "1" directly, it will accelerate my executions tremendously.

Regards

Jaraqui