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Altera_Forum's avatar
Altera_Forum
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14 years ago

Dummy Mater(WHY BUZZ)

Hi everybody!

I'm designing a hardware system(SOPC) on Quaturs 10.1. My SOPC need to add Dummy master to use.But unfortunately I don't have any information as well as use manual related to Dummy master.

Anybody and all everybody on this Forum please help me!

any information about it. I'm really desperately needed

and I'm looking forward to receive any help day in and day out

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    module dummy_master

    # (

    parameter MASTER_ADDRESS_WIDTH = 8

    )

    (

    // master clock interface

    input csi_master_clk_clk,

    input csi_master_clk_reset,

    // master interface

    output [(MASTER_ADDRESS_WIDTH - 1):0] avm_m0_address,

    output [3:0] avm_m0_byteenable,

    output avm_m0_read,

    output avm_m0_write,

    output [31:0] avm_m0_writedata,

    input avm_m0_waitrequest,

    input [31:0] avm_m0_readdata

    );

    assign avm_m0_address = { MASTER_ADDRESS_WIDTH { 1'b0 }};

    assign avm_m0_byteenable = { 4 { 1'b0 }};

    assign avm_m0_read = 1'b0;

    assign avm_m0_write = 1'b0;

    assign avm_m0_writedata = { 32 { 1'b0 }};

    endmodule