Honored ContributorHi everybody!
I'm designing a hardware system(SOPC) on Quaturs 10.1. My SOPC need to add Dummy master to use.But unfortunately I don't have any information as well as use manual related to Dummy master. Anybody and all everybody on this Forum please help me! any information about it. I'm really desperately needed and I'm looking forward to receive any help day in and day out
Honored Contributormodule dummy_master
# ( parameter MASTER_ADDRESS_WIDTH = 8 ) ( // master clock interface input csi_master_clk_clk, input csi_master_clk_reset, // master interface output [(MASTER_ADDRESS_WIDTH - 1):0] avm_m0_address, output [3:0] avm_m0_byteenable, output avm_m0_read, output avm_m0_write, output [31:0] avm_m0_writedata, input avm_m0_waitrequest, input [31:0] avm_m0_readdata ); assign avm_m0_address = { MASTER_ADDRESS_WIDTH { 1'b0 }}; assign avm_m0_byteenable = { 4 { 1'b0 }}; assign avm_m0_read = 1'b0; assign avm_m0_write = 1'b0; assign avm_m0_writedata = { 32 { 1'b0 }}; endmoduleHonored ContributorThis is the program that I've picked out at triple_speed_ethernet_design(C:\altera\10.1\nios2eds\examples\verilog\niosII_cycloneIII_3c120\triple_speed_ethernet_design)
Honored ContributorI don't understand what you are trying to do.
