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Altera_Forum
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14 years ago

Dual Port Ram problems : Synthesizes error with one or two clock signals

Hello, I was running in a problem and can't find a way out . Although there are already a lot of posts concerning problems with dual port rams, I couldn't found a solution. I am using a DE1 boa...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Feasibility of the solution depends on the used FPGA revision. With the old chips, you are stuck to single port and half RAM capacity. With recent Cyclone II parts, specifying SAFE_WRITE is mandatory to get hold of the full RAM capacity.