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Altera_Forum
Honored Contributor
15 years agoDual Port Ram problems : Synthesizes error with one or two clock signals
Hello, I was running in a problem and can't find a way out . Although there are already a lot of posts concerning problems with dual port rams, I couldn't found a solution. I am using a DE1 boa...
Altera_Forum
Honored Contributor
15 years agoHello kaz and Frank,
many thanks for the information. I was able to found a solution with your notes. True dual port ram with 2 clock is still a issue, but I could solve this issue based on my clock_domain_mux code. Works fine for me. Regards, Reinhard