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JosefH's avatar
JosefH
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1 year ago

Dual DDR connection to Agilex 5

Hello we try to find answer, and confirm by compilation, if we can connect two 1x16 LPDDR4 memories to one HSIO bank 3A in Agilex 5 SOC (each DDR connected to different sub-bank). One DDR is reserve...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

For the second bullet you mention, that applies to if you implement multiple HPS EMIFs. All of them (that you can fit; only 2 I/O banks available to the HPS) must have the same parameters. This is not required between an HPS EMIF and a separate fabric EMIF.

The answer to your question, though, is no. Bank 3A is specifically reserved for an HPS EMIF.

  • JosefH's avatar
    JosefH
    Icon for New Contributor rankNew Contributor
    1 year ago

    Thanks for your reply.

    Can you describe where this restriction is mentioned in the documentation? We found several notices regarding the EMIF and HPS-EMIF restriction, but not essentially this impossibility.

    We will try to test two alternative solutions for sharing LPDDR4 using HSP and FPGA fabric in parallel.

    The first idea is to use HPS-EMIF with dual x16 LPDDR4 in combination with an F2SDRAM bridge. We want to check parallel access F2SDRAM to one channel x16 LPDDR4 and HPS to second x16 LPDDR4.

    The second idea is to use 1x32 LPDDR4 and an interleaved access HPS / F2SDRAM bridge to two memory spaces. We want to check for possible collisions in parallel memory access and their influence on the required memory response speed.

    Does anybody have an experience with such DDR sharing?

    Thanks for your response. Josef