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Altera_Forum
Honored Contributor
Honored ContributorDriving a module output with a reg?
Hello, I'm trying to determine the best way to gain access to the output of a module which is simply a wire - who in it's own module is driven by a continuous assignment statement. The p...
Altera_ForumHonored Contributor
Honored ContributorI would simulate this logic to see if it steps through the statemachine as expected. If I had to guess the integer 'bytes_remaining' can never be set to 0 and as a result that trickles down to the CHECK_ENC_STATUS never being reachable. That was just a wild stab in the dark though, I'm not really following what's going on in the state machine since it's coded in a style that I typically avoid.
By the way you should have reset conditions for your registers.
