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Altera_Forum
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14 years ago

Driving a module output with a reg?

Hello, I'm trying to determine the best way to gain access to the output of a module which is simply a wire - who in it's own module is driven by a continuous assignment statement. The p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Whoops.. that should actually have been 15. I changed it for debugging and forgot to change it back.

With the condition set to if( sel == 15) the problem still persists.

Can you see any other anamolies in the code?

What exactly do you mean by uneqivocal condition?

Thanks,

Kristin