DRAM and SRAM with Cyclone III

Hi all,

I finalized my custom Cyclone III Board and I finally chose to connect a simple SDRAM to the FPGA (instead of the DDR). My FPGA input clock is 50Mhz.

Here are my conclusions:

interface a sdram (pc66/pc100) with cyclone iii ::

- SDRAM/FPGA Interface signals: you can use any standard I/Os pin of the FPGA for all interface signals between SDRAM and the FPGA except for the clock signal.

- Clock signal: it is recommended (not mandatory) to use a FPGA PLL output for the clock signal. By using a PLL you can easily configure the clock frequency (100Mhz for a SDRAM PC100 in my case).

- FPGA IP NiosII controller: use the standard SDRAM controller provided by Altera from sopc builder. If you choose to use your SDRAM to 100Mhz (PC100) you need to do these 3 steps:

1) Instantiate a PLL to 100Mhz (with output C1 for instance), input clock is 50Mhz in my case.

2) Instantiate a SDRAM controller with sopc builder and don't forget to select PLL output as input clock for this controller (because the SDRAM controller needs to run at the same speed than the SDRAM memory chip).

3) Tunes the PLL to adjust delays betweens the 100Mhz input clock controller and the 100Mhz PLL output which is connected to the memory chip.

interface a ddr/ddr2 with cyclone iii ::

I didn't connect any DDR/DDR2 chip on my board but I would do the following:

1) DQS/DQ interface signals: use the DQ/DQS dedicated pins from the FPGA

2) Other interface signals: can use any other I/OS of the FPGA

3) FPGA IP Nios controller: use the DDR/DDR2 Altmemphy controller provided by Altera.

interface a sram and a flash with cyclone iii ::

- I connected a SRAM and a FLASH on the same bus to the FPGA Cyclone III. Read/Write accesses to/from these memories will be based on my 50Mhz clock.

1) Instantiate a Avalon Tristate Bridge controller and configure it

2) Instantiate a SRAM controller and configure it

3) Instantiate a Flash controller (CFI in my case) and configure it

4) Connect the 2 memories to the Avalon Tristate Bridge with sopc builder

That's all Folks, now you can Generate your NiosII system... re-compile your Quartus project with the correct pinout and... GO!

I hope this post will be useful and don't hesitate to post I you find any mistake.

Best Regards,

-Pierre

Hi Pierre,

Initially you asked if there are dedicated pins for the memory interface (ALTMEMPHY). The answer is yes. Please make sure you connect your ALTMEMPHY interface to the appropriate pins. You can find these pins with the Quartus II "Pin Planner" tool. Although each I/O cell for Cyclone III is pretty much the same, the dedicated pins should give the ALTMEMPHY the best performance. Quartus II should give you an error if you are using the ALTMEMPHY and do not correctly connect the pins.

You should also turn on the "Migration" feature in the "Devices & Pins" dialog box. If you plan on moving from one device to another to reduce or increase LEs/memory/etc., you want to make sure that the pin-out you are using works for multiple devices.

Hopefully this helps.

Take care,

Christian