Altera_Forum
Honored Contributor
12 years agoDQS frequency of a Cyclone IV EP4CE40F29C8 with 2x DDR2
Hello,
A EP4CE40F29C8 (core voltage 1.2V) uses two Micron MT47H32M16 in parallel in x8 mode on bottom banks 3 & 4 creating a 32bit bus DDR2. Using ALTMEMPHY HPCII at half rate. Pin assignments are correct and it compiles fine with no errors. There are however four critical warnings concerning the four DQS pins: Critical Warning (165040): The DQS pin "DDR_DQS[3]" has a frequency of 160.0 MHz which is not supported at location PIN AF26 Info (165017): Location PIN AF26 can support a maximum DQS frequency of 134.01 MHz The same warning is given for all four DQS pins placed in: AF26, AE18, AE10, AD7 The maximum frequency quartus suggests, is the frequency when using row banks. Changing the speed grade to C7 gives the same warning with a suggested frequency of 150MHz, which is again the frequency when using row banks. According to the datasheet and the External Memory Interface Spec Estimator tool by altera, the C8 grade supports DDR2 up to 167MHz on column banks. It is not possible to run DDR2 (MT47H32M16) at 133MHz because the minimum tRTP time of 7.5ns cannot be achieved. What is going wrong here? Thnx in advance!