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Oliver_I_Sedlacek's avatar
Oliver_I_Sedlacek
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2 years ago
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DPRAM synthesised by IP Parameter Editor Pro wont compile

Moving from Quartus 20.1 Lite to Quartus 23.1 Pro I used the IP editor to generate a fresh DPRAM design, simple enough 128 words of 32 bits with separate read and write ports. Target is Cyclone 10 GX...
Programmable Logic Device
  • Oliver_I_Sedlacek's avatar
    Oliver_I_Sedlacek
    2 years ago

    So the problem was no clk62pci, which was a bit harder to fix than anticipated. A PLL was the obvious source for the development stage, but it took a while to get two IOPLLs running off the same 50 MHz input on the Cyclone 10 GX evaluation board.

    Thanks for asking the right question.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Can you show the rest of the upper level code around this instantiation? Where are clk62pci and clk100sys coming from?

Oliver_I_Sedlacek's avatar
Oliver_I_Sedlacek
Icon for Contributor rankContributor
2 years ago

So the problem was no clk62pci, which was a bit harder to fix than anticipated. A PLL was the obvious source for the development stage, but it took a while to get two IOPLLs running off the same 50 MHz input on the Cyclone 10 GX evaluation board.

Thanks for asking the right question.