Forum Discussion
Oliver_I_Sedlacek
Contributor
ContributorDPRAM synthesised by IP Parameter Editor Pro wont compile
Moving from Quartus 20.1 Lite to Quartus 23.1 Pro I used the IP editor to generate a fresh DPRAM design, simple enough 128 words of 32 bits with separate read and write ports. Target is Cyclone 10 GX...
So the problem was no clk62pci, which was a bit harder to fix than anticipated. A PLL was the obvious source for the development stage, but it took a while to get two IOPLLs running off the same 50 MHz input on the Cyclone 10 GX evaluation board.
Thanks for asking the right question.
sstrell
Super Contributor
Super ContributorCan you show the rest of the upper level code around this instantiation? Where are clk62pci and clk100sys coming from?
Oliver_I_SedlacekContributor
ContributorThis block is buried deep, but I think you've asked the key question. clk100sys comes from a PLL, no issues, but clk62pci comes from the PCIe endpoint wrapper, which is currently commented out! I'll set up a source for clk62pci and report back.
