Downloading previous versions of documents

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#  ** Error: (vsim-3010)  - Module 'sopc_system_tb' does not have a `timescale directive in effect, but other modules do.#  Region: /sopc_system_tb/dut/the_master_bfm/master_bfm

Any suggestion on how to handle this error?

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To the top of sopc_system_tb.sv add the line

`timescale 1ns / 1ps

Then Modelsim-ASE was happy for me. To build and run the code, on the Modelsim command line I used the commands;

do setup_sim.do
s
vlog -sv sopc_system_tb.sv
vsim -t ps -novopt +nowarnTFMPC sopc_system_tb
do sopc_system_tb.do
run -a 

Enjoy!

Cheers,

Dave

Many thanks again Dave. The timescale line fixed it. Yes you are right I have done only basic coding so far, nothing real world. One day perhaps... if I manage to survive all the FPGA learning. It's just that I've started learning about hardware programming around 4 months ago, but I feel that I spend most of my time learning how to use tools rather than actually doing anything productive. First it was Quartus, then SOPC, then NIOS SBT, now ModelSim.... But I guess it's the way to learn step by step.

Talking about learning, my current testbench in sv for my ST component doesn't do anything yet apart from just displaying a test message. I am trying to write an actual testbench with meaningful inputs.. be prepared for more beginner questions soon :)

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Yes you are right I have done only basic coding so far, nothing real world. One day perhaps... if I manage to survive all the FPGA learning. It's just that I've started learning about hardware programming around 4 months ago, but I feel that I spend most of my time learning how to use tools rather than actually doing anything productive. First it was Quartus, then SOPC, then NIOS SBT, now ModelSim.... But I guess it's the way to learn step by step.

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Trust me, it does not get any easier ... the tools change almost as fast as you learn them ... and then a new FPGA comes out and you have to start reading data sheets from-scratch again ...

It does make for good job security though :)

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Talking about learning, my current testbench in sv for my ST component doesn't do anything yet apart from just displaying a test message. I am trying to write an actual testbench with meaningful inputs.. be prepared for more beginner questions soon :)

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There are really two types of testbenches; interactive and automatic. An interactive testbench is one that exercises your design, but does not really check anything, eg., injects noise into a digital filter, writes the results to file, and then finishes. In this type of design, its up to you to check the results using say MATLAB to check the power spectrum. An automated testbench also checks the result, i.e., you have a "golden reference" output data file, and the testbench checks that the golden reference results were reproduced by the design. This last testbench is very useful as you don't need to look at the design once you've finished it, so long as you run the testbench, eg. using a makefile "make check" command. If you change a component that the design uses, and you break it, when you run the testbench it will fail, and you can go and fix the bug you just introduced.

Keep that in mind while designing.

Cheers,

Dave

Cheers Dave. I am doing the interactive testbench for now but I am having problems with reading the input data file. I have an array of size 153600 bytes that I save as follows in matlab:

fid = fopen('image_binval.bin', 'w');
fwrite(fid, data_image_1d,'uint8');
 

The main parts of my current systemverilog testbench file are shown below. I am just making sure the correct values are being read in. When I run it in modelsim, src_transaction.data shows the correct data values in the wavewindow until variable i reaches 57672. After that, it just displays a x in between red lines. I can't find where I am going wrong. Any help please?

`define NUMBER_OF_PIXEL_VALUES 153600 
`timescale 1ns / 1ps
 
module sopc_system_tb();
  import verbosity_pkg::*;
 
  // 50MHz clock period
  localparam time CLK50_PERIOD = (1.0e9/50.0e6)*1ns;
 
  // Clock and reset
  logic clk;
  logic rstN;
 
  // Avalon ST
  typedef logic  AvalonSTData_t;
 
  reg   storage_values ; //153600 values for 640x240 image
 
  integer fileInput, r;
 
 
  //the ST transaction is defined using SystemVerilog structure data type
   typedef struct 
  {    int               idles;  //idle is not part of Avalon ST signal, it is used in BFM only
       bit               startofpacket;
       bit               endofpacket;
       AvalonSTData_t    data;
   } transaction_struct;
 
  transaction_struct src_transaction, snk_transaction; 
  int i, j;
  // 50MHz system clock
 initial
  clk = 1'b0;
 always
 # (CLK50_PERIOD/2) clk <= ~clk;
 
  // SOPC system -Set up the Dut
  sopc_system 
  dut
    (
      .clk_0   (clk),
      .reset_n (rstN)
    );
 
 
  // Stimulus
 // ------------------------------------------------------------
 
  initial
  begin
      // Initialize input and output text files
      fileInput  = $fopen("image_binval.bin", "r");
      r = $fread(storage_values, fileInput, 0, `NUMBER_OF_PIXEL_VALUES-1); 
 
      // Initialize the BFM
      // ------------------------------------------------------------
     set_verbosity(`VERBOSITY);
    `SRC.init();
    `SNK.init();
 
      rstN = 0;
     # 50ns rstN <= 1; 
 
      // --------------------------------------------------------
      $display("Simulation Start");
      // --------------------------------------------------------
 
       for (i = 0; i < `NUMBER_OF_PIXEL_VALUES; i++)
         begin 
          @(posedge clk);
          src_transaction.idles          = 0;       
          src_transaction.data           = storage_values;
 
          if (i == 0)   
              src_transaction.startofpacket  = 1;
          else
              src_transaction.startofpacket  = 0;
 
          if (i == `NUMBER_OF_PIXEL_VALUES-1)
              src_transaction.endofpacket    = 1;
          else
              src_transaction.endofpacket    = 0;
 
       end 
   end
 
 
endmodule
 
 
 

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I am just making sure the correct values are being read in. When I run it in modelsim, src_transaction.data shows the correct data values in the wavewindow until variable i reaches 57672. After that, it just displays a x in between red lines. I can't find where I am going wrong. Any help please?

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I can't see anything obviously wrong.

However, if you just want to check that data is being read in ok, change the loop to simply display the values read from the file, eg., something like

logic  val;
for (int i = 0; i < `NUMBER_OF_PIXEL_VALUES; i++)
begin
    @(posedge clk);
    val = storage_values;
end

And display val in the wave window.

Cheers,

Dave

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And display val in the wave window.

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Yeps, I've tried that but still the same result after the counter reaches 57672. Could it be that I have reached some kind of limit with my ModelSim Starter Edition? The Altera website says the limit is 10,000 executable lines. I don't have this number of lines, but the main top module does call a few IP modules such as altshift_taps.. so it could be the case :( Can somebody please confirm this?

Assuming I get the data reading to work, I have a question related to Avalon ST this time: Is my implementation of endofpacket correct?

if (i == `NUMBER_OF_PIXEL_VALUES-1)

src_transaction.endofpacket = 1;

I am not too sure if end of packet means the end of the whole of the data to be transferred.

Also, how do I get output values from the device under test to go to snk_transaction.data?

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Yeps, I've tried that but still the same result after the counter reaches 57672. Could it be that I have reached some kind of limit with my ModelSim Starter Edition?

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Post a .zip file with source and a simulation script, and I'll try it in SE.

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Assuming I get the data reading to work, I have a question related to Avalon ST this time: Is my implementation of endofpacket correct?

if (i == `NUMBER_OF_PIXEL_VALUES-1)

src_transaction.endofpacket = 1;

I am not too sure if end of packet means the end of the whole of the data to be transferred.

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You won't break anything in simulation, so your best bet is to just try the obvious and see what happens. I haven't tested ST interfaces with the verification suite, so cannot offer any experience.

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Also, how do I get output values from the device under test to go to snk_transaction.data?

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I would look at the Avalon-ST example provided in the verification IP suite. Hopefully they show how to use the ST API and connect it to something.

I think the main thing to keep in mind, is just to try stuff, look at the waveform view, and try and clear up anything that is red. The other thing to do is look at the source code for the verification functions.

Cheers,

Dave

Thanks for your continuous support Dave. I don't think this problem is related to ASE, because I have just installed the full edition (I didn't even know we had this license!) and I still face the same problem. The error is happening with the $fread command. For example, in the following line, read_index stays at 57671 when I look at the waveform window. It's expected to be NUMBER_OF_PIXEL_VALUES-1 instead.

 read_index = $fread(storage_values, fileInput, 0, `NUMBER_OF_PIXEL_VALUES-1); 

I then tried to use $readmemb but not much luck with this either... it sent modelsim crashing when I tried to simulate it! I'm attaching the zip file which contains the simulation script(sopc_system_tb.sv) and the input data file(image_binval.bin) in folder sopc_system_sim. Could you have a go at reading the data file please? It contains 153,600 values of unsigned 8-bit integers.

Hmmm.. just forget my previous message concerning $fread. I managed to get it working by adding a "rb" instead of "r" in $fopen. Dow!! I feel so stupid :)

fileInput = $fopen("image_binval.bin", "rb");

OK, I'll start reading the Avalon ST documentation now and try things.. real work starts! Hopefully somebody with experience of ST verification will turn up on that forum soon too.

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Hmmm.. just forget my previous message concerning $fread. I managed to get it working by adding a "rb" instead of "r" in $fopen. Dow!! I feel so stupid :)

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Don't feel too bad. That's part of learning a new tool. If everything worked the first time, you'd never learn how to debug.

Cheers,

Dave