Downloading ELF Process failed of Project

Dear Daixiwen

sorry Daixiwen , I don't know your mean ...

My timing requirements problem of your mean ?

but my pll only fore clk clk_0(exteral 50MHZ) 、system_clk(100MHZ) 、

sdram_clk(100MHZ -65deg) 、 enth_clk(25MHZ).

At my sopc builder , only pll use clk_0 , other every use system_clk.

To Blcok Diagram/Schematic File , sdram_clk for sdram clk of pin

Enth_clk for Enth clk of pin , I still don't know my problem from where...