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Honored Contributor
Honored ContributorDownloading ELF Process failed of Project
Good night everybody , I have problem of QuartusII 10.1sp1 . My user chip is CycloneII EP2C35FC8 , when my sopc builder use Pll、SDRAM、FLASH、MCU、JTAG , I can run...
Altera_ForumHonored Contributor
Honored ContributorDear Daixiwen
sorry Daixiwen , I don't know your mean ... My timing requirements problem of your mean ? but my pll only fore clk clk_0(exteral 50MHZ) 、system_clk(100MHZ) 、 sdram_clk(100MHZ -65deg) 、 enth_clk(25MHZ). At my sopc builder , only pll use clk_0 , other every use system_clk. To Blcok Diagram/Schematic File , sdram_clk for sdram clk of pin Enth_clk for Enth clk of pin , I still don't know my problem from where...
