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fzliu's avatar
fzliu
Icon for New Contributor rankNew Contributor
7 years ago

Does the MAX V CPLD support non-standard (e.g. 2.8V) VCCIO voltages?

We have an IoT application that utilizes the MAX V CPLD. Due to nuances in the design, non-negligible power savings will occur if we are able to step down from the standard 3.3V to a non-standard 2.8...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Since the MaxV CPLD only supports 1.5V/1.8V/2.5V/3.3V , you may have to set the Bank Vccio voltages to 2.5 and use an external resistor to drop the voltage down to 2.5 volts at the inputs. The FPGA pins/banks will may not be able to tolerate 2.8V when set to 2.5V.

As for using 3.3V Vccio, when you drive 2.8V signal into the IO pins, there's a possibility that logic 1 may not get read correctly ( difference of .5V).