Honored ContributorIs it mandatory to connect the FPGA clock pins to clock source. I am implementing USART in the fpga which is driven by synch clock and data given to thE I/O pins of FPGA. kindly help??
Honored ContributorAn "extra" clock over that of your USART is not mandatory, but it would be advised.
Your USART will have a clock sure, but it will be a very slow clock. It is probably too slow for use as a PLL reference clock. Perhaps you could provide a little more detail on what you are trying to design, and what else this FPGA might end up being used for? If you are designing some form of glue-logic between your USART and another component, then a CPLD might be more appropriate, and you might not need a clock dedicated to the CPLD internal logic. For example, you could easily implement an SPI slave device using just the clock that comes with the SPI interface. However, why limit yourself? If your FPGA has a clock, then it can monitor the USART for activity, you can implement a SignalTap II logic analyzer and trace your USART transactions, you can implement a processor to interface to your USART ... etc. Cheers, Dave
