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xytech's avatar
xytech
Icon for Contributor rankContributor
6 years ago
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Does A10 GX device's banks need individual clocks input from the dedicated CLK pins for DDR4 ?

Hi, there, we use A10 GX(10AX057H3F34E2SG) for one DDR4 SO-DIMM mempry card. bit width 64, and three FPGA banks are used. In our previous experience for DDR3, these banks do not necessarily need t...
  • NurAida_A_Intel's avatar
    NurAida_A_Intel
    6 years ago

    Hi xytech,

    Thank you so much for the details clarification. It really helps to understand the issue better.

    Yes, your understanding is correct. Since the current clock source is not a dedicated to the PLL that you want to use with your DDR4, then you need to add another clock device to feed the ref_clk. Please note that using additional clock will slightly give effect to the clock jitter and timing margin which also mentioned in the handbook.

    Thanks

    Regards,

    NAli1

NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi xytech,

Thank you so much for the details clarification. It really helps to understand the issue better.

Yes, your understanding is correct. Since the current clock source is not a dedicated to the PLL that you want to use with your DDR4, then you need to add another clock device to feed the ref_clk. Please note that using additional clock will slightly give effect to the clock jitter and timing margin which also mentioned in the handbook.

Thanks

Regards,

NAli1

xytech's avatar
xytech
Icon for Contributor rankContributor
6 years ago

Thanks, NAli1.

By the way, may I ask how do Intel employee responds to different questions in different sections of forum? For example, someone posted two questions on two seperate thread about A10 GX device and Cyclone 10 LP device, will there be specific Intel personel to deal with them respectively according to devices families, or just handle these questions randomly if any intel gyus read the new threads? Thanks.