Forum Discussion
Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- For me, the MAX was not in HZ state with weak pull-up (as it is during configuration by Blaster), because some of its IOs driving LED or ON/OFF of board power supplies were in relevant state. But the configuration of the FPGA by the MAX PFL was failing, even after OFF/ON of the board. --- Quote End --- If MAX II wasn't defective (worked again after reprogramming), the observation indicates that there's no effective configuration consistency check implemented. The configuration bitstream CRC check would prevent a Cyclone FPGA from entering user mode (within the reliability of the respective CRC length).