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If the configuration consistency is checked, I would expect MAX II staying in unconfigured state (all pins tri-stated with weak pull-up), otherwise it might show arbitrary erroneous behaviour. Did you remember the behaviour in this single evident?
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For me, the MAX was not in HZ state with weak pull-up (as it is during configuration by Blaster), because some of its IOs driving LED or ON/OFF of board power supplies were in relevant state. But the configuration of the FPGA by the MAX PFL was failing, even after OFF/ON of the board.
Usually, the external CFI FLASH containing FPGA firmware pages is corrupted, but in this case the only way to recover was to reconfigure the CPLD CFM.
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Regarding FPGAs, at least Cyclone III documentation seems to indicate there is some kind of error checking during configuration but again the details aren't included.
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You could find some intersting litterature about SEU mitigation in this ALTERA documents :
http://www.altera.com/literature/wp/wp-01135-stxv-seu-mitigation.pdf http://www.altera.com/literature/wp/wp-01135-stxv-seu-mitigation.pdf you could also find more docs on the ALTERA website with the "SEU mitigation" search keywords ;-)
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