DMA reading multiple PIOs

Jake,

Yes, that is what I suspicioned all along, i.e. that you cannot just pass the base address for the first PIO in and expect it to read the other PIOs. When I saw the address range for each PIO, I did not think the approach I presented would work, but I just wanted someone to verify it was for the reason I suspected.

The reason for trying to use the DMA in the first place is to speed up the reading cycle, but from what you have indicated, this will not get me there…

I have also been thinking about increasing my system/memory clock frequency (being generated by the Altera PLL). I have actually tried to do just this, but my system will not accept the program from the debugger…

My input clock is running at 50 MHz, and I am using the PLL to run at 85MHz. Everything works fine. I am using a Cyclone II EP2C70F896C6 FPGA, and the Cypress CY7C1380D SRAM which will go up to 167 MHz, so unless I have some layout problems on my board, I should be able to increase the frequency out of the PLL, but so far, I have had no luck. My current settings are;

Freq In – 50 MHz

PLL multiplier = 17

PLL divisor = 10

Phase Shift = -4.80 ns

I believe that I should be able to go up to 141.667Mhz using;

Freq In – 50 MHz

PLL multiplier = 17

PLL divisor = 6

Phase Shift = -?.?? ns

After talking with the Altera My Support folks, I have tried several phase shift values. Altera said that is should be the 90 degree value depending on the frequency you are trying to generate (e.g. at 141.666667 MHz, => (1/141.66667MHz) * (0.25) ~= -1.76ns) but this did not work. Any suggestions on either another phase shift value, or another area to look at. Thanks much for your help.

Fred