New Contributor
ContributorHi,
Thanks for your question. You may check out this white paper:
It made references to some very old CPLD products that we have but the basic principles still apply.
For the list of the newer CPLDs, you may visit this page:
https://www.intel.com/content/www/us/en/products/details/fpga/max.html
-Hazlina
New ContributorHi Hazlina,
Thank you very much for your prompt reply. That old white paper was a great reference for me. The CF+ to uC interface is one of the applications I have in mind for a project. I wanted to do bridging between ATA/IDE and another bus and the CPLD as a companion to uC seems a best fit for that application because CF is implemented in true IDE mode. I believe the merger between ALTERA and Intel makes it indispensable source for any designer who wanted to tap into a plethora of design examples without them reinventing the wheel. It seems diving into the world of programmable logic is inevitable for me.
Well, I didn't see any reference to the DMA controller implementation on a CPLD or FPGA in the white paper. Anyways, in reference to AN495 (IDE/ATA controller) on MAX 10 series, the scenario I have in mind is to use the Nios II embedded processor IP core in addition to the IDE/ATA controller core and the DMA controller core in one single device without a microcontroller. However, I'm still unsure if this scenario is possible and whether I can achieve the DMA controller aforementioned above with proper DREQ/DACK signaling so I can use it to move data between the ASIC and the microcontroller.
Any comment is highly appreciated!
Zaher
