Honored Contributor
Honored ContributorHi Grinder:
I feel your frustration. But don't give up. First off FPGA's are extremely flexible devices, so the NIOS core (microcontroller), is not "IN the FPGA" as a hard core in so much as it is built out of the FPGA fabric. So that in itself shows you the flexability of the device. I'm not very familiar with this particular development board, but if it follows the trend of others I worked with, most of the documentation, and support was done with a particular version of Quartus. Unfortunatly, Quartus is a moving target, so things get broken along the way, and the developers on the boards don't always spend the time, to update the projects. There were significant changes between quartus 9.x and 10.x, so many things broke. Also a common issue, is the versions of cores they used change between versions, so when you try to run it will say core xxx version y.y is not available. Most of the time, you can just replace that version in QSYS with the latest and move on. As far as creating verilog to work with the micro. The common way is to make your own QSYS core that has an avalon bus interface. This is not a simple project, but gives you a memory map interface that you can then plunk into QSYS and build. You can use all kinds of other interfaces to get the job done. (IE a serial interface, toggling GPIO's etc), but for efficiency of transfers, the Avalon bus is the way to go. If you are looking to use a more powerful CPU, Cyclone V have ARM A9 cores available (HARD cores built into the fabric). Then using ARM's AXI or APB bus structure is the way to go. The Avalon specification is found at http://www.altera.com/literature/manual/mnl_avalon_spec.pdf Best of luck. Pete
