Honored Contributor
Honored ContributorThe automatic scaling - as explained in your document - is meant to keep the data values at full representation of 16 bits. i.e. there is variable gain control (similar to AGC)depending on input values. Obviously the document doesn't tell how they have implemented that but there might be a comparison and a mult/div stage inside.
edit: the diagram obviously indicates *2^n and divide by 2^m by the automatic scaling unit. . the n/m values can be arrived at by checking the values of every bit and its index for num/denum then it is possible to target a result that equals +2^15-1 by shifting num/denum right or left. It seems you have 16 samples per symbol at divider output(since there is a decimation factor of 16 afterwards). If they are looking at values within one symbol window of time to adjust the representation to 16 bits then it gets more difficult to scale. , if not then all you need is to scale every positive value up and every negative value down. This scaling is really vague to me, so is the modulation, is it FM or FSK?
