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TBaki's avatar
TBaki
Icon for New Contributor rankNew Contributor
6 years ago

Divider IP for EP3C55F484I7

I am using Cyclone III FPGA (EP3C55F484I7) for my design and Quartus II version 10 software. In my RTL design, I am using division logic (signed data / integer). Currently, I am using / operator an...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

You can try on the LPM_DIV on Q13.1 usually, it should not have problem on the timing closure if you use the IP provided.

Let me know if you still face problem after using the IP.