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TBaki's avatar
TBaki
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5 years ago

Divider IP for EP3C55F484I7

I am using Cyclone III FPGA (EP3C55F484I7) for my design and Quartus II version 10 software. In my RTL design, I am using division logic (signed data / integer). Currently, I am using / operator an...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

There should be an LPM_divide megawizard for you to be used. Can you double check on this.

Also, I would suggest you use the Q13.1 version that last support CIII

Your frequecies running is not high. can you attached your design.qar for me to look into the violation. Basically, you will need to go though the training before do timing closure.

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1116.html?wapkw=timing%20training

you may click on the follow on and Prerequisites link as well.

  • TBaki's avatar
    TBaki
    Icon for New Contributor rankNew Contributor
    5 years ago

    LPM_DIV is not there in the Quartus 10. I will check in 13.1. Sorry, I can't share you the qar as it is custom project. Briefly i can explain like from ADC data is acquired in signed format. Then this signal is multiplied with integer constant and then divided by a integer constant. When I ran STA, there is a huge data delay from F/F output of Multiplier to F/F input of Divider. The delay is 216ns. so slack is about -172ns.