Distinguish the pulse issue

So, there are a couple of ways you can do this. To satisfy the Nyquist criteria you need at least a 250Mbps sampling rate. However, I think you'll want to get the resolution of the samples as high as you can. Here are two options:

1 - Run the sampling clock as high as you can and use double data-rate I/O to double the sampling rate. So for example, if you run the FPGA clock at 500MHz (this can be done in Stratix II or higher), then use the DDIO inputs of the registers to get an effective sampling resolution of 1ns. You can then do some simple comparisons to see if two pulses occurred within 8ns.

2 - If you are going to use a slower FPGA with a slower clock, use a PLL to create multiple phases of the clock. So if you run the clock at 200MHz with 5 equally spaced phases, you also get an effective 1ns sample resolution. You'll need to do some clock resynchronization and you'll want to manually place the input registers to assure minimum skew between the samples.

3 - You could simply run at the minimum 250Mbps sample rate. Obviously your chance of error increases.

Jake