Discrepancies between datasheets and technical documentation regarding FPGA configuration.

Thanks for your reply

I think so too.
Your opinion has gave me confidence in my thinking.
But tDSU and tSU has different value in Arria V data sheet.
tSU value is 1.5nsec at AS configureation section and tDSU value is 5.5nsec at PS configureation section.
And, these paramaters has diffarent memo as follows.
tSU : Data setup time before the falling edge on DCLK
tDSU: DATA[] setup time before rising edge on DCLK

I realized the probrem is an explanation method for tSU is tDSU in AS configurasion section.

Thank you for your help.