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I assume (with your current implementation) you are adjusting the outgoing data, by a full clock cycle, every time you detect a 'change' to the incoming HSYNC pulse timing.
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I will copy the full code here later when I get home. But basically I have a framebuffer and I control the incoming hcount and vcount by waiting the hsync and vsync (they are positive pulses in this case) like
process(CLOCK_25)
begin
if (rising_edge(CLOCK_25)) then
hblank <= '1';
if (HSYNC_IN = '1' and hcount >= 655) then
hblank <= '0';
end if;
end if;
end process;
process(CLOCK_25)
begin
if (rising_edge(CLOCK_25)) then
if (hblank = '0') then
hcount <= 0;
else
hcount <= hcount + 1;
end if;
end if;
end process;
Being CLOCK_25 the 12Mhz clock. Then I use hcount together the vcount to calculate the offset in the pixel array to store it.
The VGA output has it's own 25Mhz clock and since it's buffered, it doesn't rely on the incoming hsync, vsync. It just pumps out whatever is in the buffer.
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