digital simulation model for Altera SoC (Arria 10)

I don't think Altera provides a full SoC model. I would assume that it might be possible to gather some of the pieces like the core from ARM and the DesignWare components from Synopsys, but that would probably come with a hefty price-tag. Altera could provide their RTL in encrypted or compiled form somehow if they have a license to do so.

I think your best bet will be to use AXI BFM's and/or UVM models and stimulate your FPGA fabric logic from there.

Another option I've been thinking about is run an open source emulator like qemu under VPI/PLI. Then run the binary code under qemu and make some hooks to map to memory access to the FPGA fabric to AXI cycles. I've done this for a MIPS emulator in the past, but it's a considerable amount of work. Further, this will not get you models for the EMAC, SPI, and other specific hard functions found in the Arria 10 SoC. On the other hand qemu can run Yocto Linux today so it's quite capable.