Forum Discussion

NBK's avatar
NBK
Icon for New Contributor rankNew Contributor
2 years ago

Digital input slew rate or rise time, fall time requirements for 10M16SCU169I7G

Hello, Does 10M16SCU169I7G FPGA has any constraints for DIgital input slew rate or maximum allowed rise/fall times. if yes, what are the maximum allowed limits? Thanking you in advance.
Configuration
NBK's avatar
NBK
Icon for New Contributor rankNew Contributor
2 years ago

Thank you very much for the reply.