Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Diffrerential Pins topology

Hi I want to interface my FPGA to a DAC using LVDS Standard. The problem is, that the FPGA and DAC pins topologies are not the same. Each FPGA positive pin cannot be directly (physically) conne...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It's not exactly forbidden to use vias for a 400 MBps connection, you can use them even for GBit interfaces. Typically, longer differential traces are run in a screened inner layer, so you have at least a pair of vias at each end. They can be used to invert the polarity as well. But I agree, that you should avoid vias if possible. If you have only a short connection on the top layer, I would also invert the driving nets inside the FPGA, as rbugalho sugested.