different width dual port ram from VHDL template

I think what is missing from this discussion is how a block of ram is designed to support variable width.

My view is that a ram block and depending on device will support a list of width Vs size and I know for example stratix iv M9Ks support up to 36 bits width... how? possibly through some extra logic inside ram block itself.

Any more width request requires that several blocks are aligned together plus extra logic from fpga fabric to bridge across the two different widths, say logic from short side muxed into wider bus then connected to all ram blocks in parallel. This is where substantial ram waste may occur.