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Altera_Forum
Honored Contributor
Honored Contributordifferent width dual port ram from VHDL template
Dear all, In my design I have a dual port memory, where the write port is 128x32 configuration and read port is 4096 x 1. I have written the module in the VHDL, but my implementation results in...
Altera_ForumHonored Contributor
Honored ContributorTemplates to infer dual port RAM with ports of different width can be found in the Quartus Software Handbook. I don't see a reason to doubt it's correct operation, although I implemented similar design previously by instantiating altsyncram in my VHDL code directly (I didn't know how to infer it). The selection of different RAM types by synthesis attributes is also discussed in the Software Handbook.
--- Quote Start --- variable bitwidth demands too much memory blocks especially if it is read/write on both ports, check your resource and you will see. --- Quote End --- As long as the implemented bitwidths are within the supported range of the respective RAM type, there should be not a single RAM cell wasted. At least I didn't observe this in my RAM designs. --- Quote Start --- but why that? If the serializer logic forms a part of the m4k cell, there should be advantage of using the onchip logic rather than generating my own. --- Quote End --- Yes, that's why the different width feature is offered by Altera.
