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Altera_Forum
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14 years ago

Different value during synchronic reset

Hi,

I’m working with Cyclone 3 FPGA and I would like to know whether during asynchronic reset*, it’s allowing to set “std_logic/ std_logic_vector” to value that different from ‘0’/ x”00” accordingly (let’s say: x”A5” for the second one…)? (The code passes both full compilation and simulation)

Is that kind of writing will consider as a good writing style?

In addition to the answer, can I find the explanation to the relevant issue from the Handbook?

*before the “elsif clk’event and clk=’1’ then”…

Thanks,

Idan

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    That's perfectly fine. Note that registers always reset to 0. When you write code like that, synthesis will put a not gate before and after the register. So now when you reset the register to 0, that 0 gets inverted and looks like a 1 to the rest of the world. Any logic value driving that register gets inverted on the way in and inverted on the way out. So though it powers up to 0, the rest of the design thinks it power up to 1.

    Also, the additional not gates can be absorbed into most logic(LUTs for example) for free, so you don't take an area/speed hit. The only place it's hard to absorb them is on the I/O registers because there is no LUT, and I believe on most devices those are the only registers that actually can be reset to 1. (It's been a while since I last confirmed this, so not sure). If you write that code and it goes through synthesis, you can be sure it's right.

    The only major gotcha is if you probe the register with SignalTap or look at it in a post-fit simulation. In these cases, you're looking at the register directly and it will behave the exact opposite of what you expect. If you know about the inversion(and I think there's a table in the .map.rpt that shows which ones get this), then you know it's fine, but I've seen a few people get confused by a register acting the opposite of what they expected.