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Parkavi's avatar
Parkavi
Icon for New Contributor rankNew Contributor
4 years ago

Different behavior of FPGA on power cycle-Cyclone v FPGA(custom board)

Hi, I have a design with Cyclone v transceiver native phy IP. Logic receive UART data and framing it with header, tailer and sending it to IP.IP send it serially to SFP fibre cable which is loopba...
NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
4 years ago

I’m glad that your question has been addressed. Thank you for sharing your solution with the community. I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.