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Parkavi
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4 years ago

Different behavior of FPGA on power cycle-Cyclone v FPGA(custom board)

Hi, I have a design with Cyclone v transceiver native phy IP. Logic receive UART data and framing it with header, tailer and sending it to IP.IP send it serially to SFP fibre cable which is loopba...
Parkavi's avatar
Parkavi
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4 years ago

Hi Aiman,

My problem got resolved.

1. In manual word aligner mode, i manually drive rx_walign port when i sent word align pattern. In this case ,the above null issue was resolved.

2.As i said before, in sync_sm mode i found corruption in data packets. That was resolved by setting rx word align pattern as 17C in IP configuration , enabled 8b/10b encoder and decoder ,driving tx_datak port from rx_syncstatus which is inverted and given.And transmitting BC to IP.

Thank you for your support!!!!