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Parkavi
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4 years ago

Different behavior of FPGA on power cycle-Cyclone v FPGA(custom board)

Hi, I have a design with Cyclone v transceiver native phy IP. Logic receive UART data and framing it with header, tailer and sending it to IP.IP send it serially to SFP fibre cable which is loopba...
Parkavi's avatar
Parkavi
Icon for New Contributor rankNew Contributor
4 years ago

Hi sir,

1.Tried with new quartus version but issue is not fixed.

2.The design without IP(transceiver native phy) is working fine on power cycle. But only with IP we are facing this problem. Even with IP,RX word aligner mode is in sync_sm mode, we didn't face this kind of issue but we faced data corruption in that mode. So we tried to use bitslip mode ,there is no data corruption but this null issue is occurring occasionally on power cycle.

Please guide us to move forward!!!

Thank you!!