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Parkavi's avatar
Parkavi
Icon for New Contributor rankNew Contributor
4 years ago

Different behavior of FPGA on power cycle-Cyclone v FPGA(custom board)

Hi, I have a design with Cyclone v transceiver native phy IP. Logic receive UART data and framing it with header, tailer and sending it to IP.IP send it serially to SFP fibre cable which is loopba...
NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi,


  1. Can you try to program by using the latest version of Quartus lite which is 21.1 to see if you get the same problem?
  2. Also, please try to create a simple design, convert into JIC and then program it. Then try to power cycle. Do you get the same problem?


Regards,

Aiman