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Parkavi's avatar
Parkavi
Icon for New Contributor rankNew Contributor
4 years ago

Different behavior of FPGA on power cycle-Cyclone v FPGA(custom board)

Hi, I have a design with Cyclone v transceiver native phy IP. Logic receive UART data and framing it with header, tailer and sending it to IP.IP send it serially to SFP fibre cable which is loopba...
NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi,


What is the Quartus version that was use? Can you try with the latest Quartus version?

Also what do you mean by null data? Any error shown? Please provide a screenshot.


Regards,

Aiman