Forum Discussion

Parkavi's avatar
Parkavi
Icon for New Contributor rankNew Contributor
4 years ago

Different behavior of FPGA on power cycle-Cyclone v FPGA(custom board)

Hi, I have a design with Cyclone v transceiver native phy IP. Logic receive UART data and framing it with header, tailer and sending it to IP.IP send it serially to SFP fibre cable which is loopba...
Parkavi's avatar
Parkavi
Icon for New Contributor rankNew Contributor
4 years ago

Hi sir,

Thank you for your response. i am new to this Transceiver Native IP. Yes we had done the configuration based on these documents only and with this we are able to get the right data most of the times during power cycles. Occasionally we see there is null data during such power cycle. Any suggestion on what could be the cause for such occasional erratic behavior? Which configuration of IP need to be relooked in this case? Please advice.

Thank you!!