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As we know "
logic" data type has 4 states = 0, 1, X & Z
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std_logic data type has 9 states: "U, X, 1, 0, Z, W, L, H, - "
u: Uninitialized
x: Unknown
1: Logic 1
0: Logic 0
Z: High impendance
W: Weak signal, can't tell if it should be 0 or 1
L: Weak signal that should probably go to 0
H: Weak signal that should probably go to 1
-: Don't care.
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In this is example I have use bit as datatype for
clk and
reset_n signal. because it is obvious that clock can not be X or Z.
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In your example, U state can be useful if you forget to initialize a signal in your component testbench.
Honored Contributor
