New Contributor
New ContributorI use two input pins on fpga: input_clock, input_data.
Both signals are generated by the same external chip (ADC).
Data arrives on the input pin 3ns before clock arrives, and stays valid for 1ns after. This is according to datasheet of the external chip, and this is what I observe on the scope.
Clock frequency is 50 MHz. PCB traces are very short and equal length.
I'm not using PLL, I just use clock from the clock pin directly.
So, the calculations are very simple:
50MHz = 20ns
min = 1ns
max = 20ns-3ns = 17ns
SDC file:
create_clock -name input_clock -period 20 [get_ports input_clock]
set_input_delay -clock [get_clocks input_clock] -min 1 [get_ports input_data]
set_input_delay -clock [get_clocks input_clock] -max 17 [get_ports input_data]
Occasional ContributorOn the assumption that the constraints are correct, have you checked the Timing report file to ensure that it was able to meet your constraints? (I.e. no negative slack shown in red for that clock?)
