JSmit123New Contributor7 years agoDid I set up input timing constraints correctly? I have both clock and data coming from external chip: input_clock, input_data. Datasheet says setup time 3ns, hold time 1ns. Can you please check if these constraints are correct? I believe so but t...Show More
KennyT_alteraSuper Contributor7 years agoYou can refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf page 9
Recent DiscussionsWorst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)Cannot access SSLC portal for Questa LicenseWhy does PTA show zero W for F-tiles in Hierarchical Design EditorFPGA ECCN RequestAGRW027R28A2I2V Thermal Model