Did I set up input timing constraints correctly?

You asked if your constraints were correct, and as I mentioned, they're not. Unfortunately, they're not that simple. This is a source synchronous interface so you have to do things a bit differently.

As I said, you need a virtual clock to correctly set up the relationship between launch and latch edge. That may be optional for other types of interfaces (though it's highly recommended), but with source synch, it's basically required to set up the relationship correctly. What are the properties of the clock that is driving this ADC device? And what is the relationship between that device's input clock and its output clock?

It sounds like the datasheet is giving you a tco or skew specification between the clock and data, but it is odd that the data is launched before the clock, unless this is meant to be a center-aligned clock (though not truly center aligned since it's only 3 ns past the data edge instead of 10. What is the name of the spec for this that it is giving you?

I highly recommend you check out that online training. Also, seeing a timing report of what you're getting with your existing constraints may help.

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