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ContributorHi JSmit123!
First of all, it's strange that you mention datasheet setup and hold params, because in your case as I understand your FPGA receives signal. So I you want sombody to help you you need to add detailed description of your system.
For now I can say that your constraints are wrong.
I think that you have an external device (let it be ADC), and it outputs Source Synchronous data, so to properly latch data on FPGA you need to use one of the Source Synchronous methods.
You can use PLL in sourse synchronous mode, for example.
Hope that helps.
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Best Regards,
Ivan
ContributorHi JSmit123!
I agree with sstrell last post, it is not a simple task, so you need some reading for deeper understanding of Source Synchronous Interface Constraints.
In my opinion best resourse on that topic - https://fpgawiki.intel.com/wiki/index.php?title=File:Source_Synchronous_Timing.pdf by Ryan Scoville.
To write a proper sdc constraints in your case you can choose from number of methods.
Hope that helps.
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Best Regards,
Ivan
